##########################################################
# Generated by: Cadence Encounter 13.10-p003_1
# OS: Linux i686(Host ID patrice)
# Generated on: Thu Jun 15 23:38:19 2017
# Design: /TD>accu
# Command: summaryReport -outdir summaryReport
##########################################################

Design Summary Report

General Design Information
Design Status
 Routed
Design Name
 accu
# Instances
 129
# Hard Macros
 0
# Std Cells
 129
# Pads
 0
# Net
 49
# Special Net
 2
# IO Pins
 18
# Pins
 108
# PG Pins
 258
Average Pins Per Net(Signal)
 2.204

General Library Information
# Routing Layers
 5
# Masterslice Layers
 4
# Pin Layers
 5
# Layers
 14
# Pins without Physical Port
 0
# Pins in Library without Timing Lib
 101
# Pins Missing Direction
 0
Antenna Summary Report
 For more information click here
# Cells Missing LEF Info
 0
# Cells with Dimension Errors
 0

Netlist Information
# HFO (>200) Nets
 0
# No-driven Nets
 0
# Multi-driven Nets
 0
# Assign Statements
 0
Is Design Uniquified
 YES
# Pins in Netlist without timing lib
 29


Internal
 External
No of Nets
 47
 0
No of Connections
 79
 0
Total Net Length (X)
 1.2417e+03
 0.0000e+00
Total Net Length (Y)
 1.5420e+03
 0.0000e+00
Total Net Length
 2.7837e+03
 0.0000e+00

Timing Information
# Clocks in design
 0
# Generated clocks
 0
# "dont_use" cells from .libs
 0
# "dont_touch" cells from .libs
 0
# Cells in .lib with max_tran
 0
# Cells in .lib with max_cap
 0
# Cells in .lib with max_fanout
 0
SDC max_cap
 N/A
SDC max_tran
 N/A
SDC max_fanout
 N/A
Default Ext. Scale Factor
 1.000
Detail Ext. Scale Factor
 1.000

Floorplan/Placement Information
Total area of Standard cells
 6210.000 um^2
Total area of Standard cells(Subtracting Physical Cells)
 4464.000 um^2
Total area of Macros
 0.000 um^2
Total area of Blockages
 0.000 um^2
Total area of Pad cells
 0.000 um^2
Total area of Core
 6226.875 um^2
Total area of Chip
 78179.805 um^2
Effective Utilization
 1.0000e+00
Number of Cell Rows
 5
% Pure Gate Density #1 (Subtracting BLOCKAGES)
 99.729%
% Pure Gate Density #2 (Subtracting BLOCKAGES and Physical Cells)
 71.689%
% Pure Gate Density #3 (Subtracting MACROS)
 99.729%
% Pure Gate Density #4 (Subtracting MACROS and Physical Cells)
 71.689%
% Pure Gate Density #5 (Subtracting MACROS and BLOCKAGES)
 99.729%
% Pure Gate Density #6 (Subtracting MACROS and BLOCKAGES and Physical Cells)
 71.689%
% Core Density (Counting Std Cells and MACROs)
 99.729%
% Core Density #2(Subtracting Physical Cells)
 71.689%
% Chip Density (Counting Std Cells and MACROs and IOs)
 7.943%
% Chip Density #2(Subtracting Physical Cells)
 5.710%
# Macros within 5 sites of IO pad
 No
Macro halo defined?
 No

Wire Length Distribution
Total metal1 wire length
 219.9000 um
Total metal2 wire length
 1453.9500 um
Total metal3 wire length
 943.8750 um
Total metal4 wire length
 93.0000 um
Total metal5 wire length
 105.6000 um
Total wire length
 2816.3250 um
Average wire length/net
 57.4760 um
Area of Power Net Distribution
 For more information click here